During the formation of semiconductor devices such as dynamic random access memory (DRAMs), static random access memory (SRAMs), microprocessors, etc. insulating layers such as silicon dioxide, phosphorous-doped silicon dioxide, silicon nitride, etc. are used to electrically separate conduction layers such as doped polycrystalline silicon, aluminum, refractory metal silicides, etc. It is often required that the conduction layers be interconnected through holes in the insulating layer. These holes are referred to as contacts or vias and often must exhibit specific characteristics such as a sloped or tapered profile. The sloped profile is necessary so that the step coverage of the conduction layer into the hole is of adequate thickness. Standard techniques for deposition of the conduction layers include sputtering and evaporation. Both of these techniques provide step coverage of the contact hole that is sensitive to the contact profile. Vertical contact profiles often result in unacceptable step coverage. Highly sloped contact profiles result in good step coverage, however, the contact is often excessively enlarged in this process. This enlargement may cause unwanted electrical shorting between or within conduction layers, and may also reduce the density of the circuit features, that is, limit how close together the devices can be placed.
Providing adequate contact slope is critical to achieving acceptable contact step coverage. Several methods of producing sloped contacts are known. These can be grouped into the general categories of wet etch, wet/dry etch, reactive ion etch (RIE), isotropic/RIE etch, and resist erosion technique.
The wet etch technique uses standard photoresist exposure and development techniques to print the required contact pattern on the insulating layer. To further enhance the slope of this process, CF.sub.4 /O.sub.2 plasma pretreats have been used to promote preohmic taper. The plasma pretreat is difficult to control and provides non-uniform tapers. The profile of the sides of the photoresist opening are vertical for this type of etch. As the insulating layer is etched, with NH.sub.4 F:HF acids of the like, the photoresist will protect the areas not exposed. The chemical wet etch will etch the insulating layer isotropically so that the contact profile is sloped. This process significantly enlarges the contact area due to the nondirectionality of the wet etch. In addition, the acids used suffer from high particulate counts which contaminate the contact area.
The wet/RIE technique process has the disadvantage of requiring two separate etch processes and still uses the acid as in the wet etch. To create an initial slope profile followed by a less sloped profile in the oxide contact (funnel shaped preohmic), two photoresist steps are used each requiring a different acid and/or dry etch to accomplish each objective. Problems resulting from this process include: resist adhesion and phosphorous concentration differences on the oxide surface that cause erratic size and taper of preohmics; excessive undercutting of the preohmics caused by variations in the acid strength from batch to batch, changes in buffering concentrations inherent in the acid solutions (crystals), enhanced etch rate at stress locations, and temperature variations, and; alignment tolerances required result in significant photoresist redo rates.
The isotropic/RIE etch technique first etches the contact pattern delineated by the photoresist into the underlying glass substrate using a high pressure isotropic plasma etch (CF.sub.4, 8.5%). The etch is completed with a selective RIE etch step to remove the remaining oxide. The isotropic step of this method is described in U.S. Pat. No. 4,361,599 issued to Robert L. Wourms. This technique results in a cusp shaped taper rather than a sloped taper, may have decreased process stability, and may require additional handling.
In the resist erosion technique, the required contact pattern is printed on the insulating layer, again using standard photoresist exposure and development techniques. Next, the photoresist layer in baked such that the resist flows giving the walls defining the openings in the resist a tapered or sloped profile. Next, the device is dry etched in an environment that will etch the substrate and the resist at the same time. This will replicate the sloped resist profile into the substrate. The disadvantages in this process are that a relatively thick resist layer is required, the scaling of the process does not lend itself to very large scale integration geometries, and the reproducibility across one or more wafers of the particular slope of the baked resist is very poor.
Another type of the resist erosion technique uses resist faceting. First, standard photoresist exposure and development techniques are again used to print the required contact pattern on the insulating layer. A dry etch of the oxide is then conducted using an in situ resist tapering process. By using a low pressure and high oxygen flow etch, the corners or edges of the resist will etch faster than the planar resist. This results in a sloped resist profile referred to as resist faceting. This slope is then replicated into the substrate using the same technique described for the resist erosion technique.
Another form of resist erosion technique is a two step method and uses a two-layer photoresist mask. This is described in Saia, et al., "Dry Etching of Tapered Contact Holes Using a Multilayer Resist", J. Electrochemistry Soc.: Solid-State Science and Technology v. 132 (August, 1985). Here the authors describe the process using a two-layer photoresist mask, where the bottom layer is poly (methyl methacrylate) (PMMA) and a plasma gas etch containing CHF.sub.3, argon and oxygen. The photoresist to oxide etch rate ratios ranged from 1.5:1 to 1:1.
One of the drawbacks of resist faceting techniques is the limit of the taper produced in the substrate. In order to achieve an appreciable sloped resist profile, a large amount of the resist must be consumed during the faceting step. This resist consumption requires both thickening of the resist and limiting of the of the facet etch time, which is approximately one-half of the total etch time, to prevent resist break through and etching to areas once protected.
The faceting process increases the contact size delineated by the resist prior to the final etch step that removes remaining dielectric. The disadvantages of this technique include the enlargement of the base of the contact beyond the original size delineated in the resist. The final facet etch step, that is required to clear the oxide, will tend to destroy the slope character of the contact.
In general, as devices and line widths have become smaller, wet etching has proved unsuitable for fine line etching below about 3 .mu.m. In addition, profile control has also driven the industry in the direction of plasma (dry) etching. Overviews of etching are reported in Weiss, "Plasma Etching of Oxides and Nitrides", Semiconductor International, p. 56 (February, 1983) and in Coburn, "Pattern Transfer", Solid State Technology, p. 117 (April, 1986).
An article by Bergendahl et al., "A Flexible Approach for Generation of Arbitrary Etch Profiles in Multilayer Films", Solid State Technology, 107 (November, 1984), describes an additional method known as multistep contour (MSC) etching. MSC is describes as combining independently optimized process modules to form a complete process. The process described in the Bergendahl article has the problems of filament development and excessive bulk resist removal, and stresses induced by power pulses during all process steps.
While the ideal contact through a dielectric layer between two conduction layers would be a completely metal filled truly vertical contact hole or via, technology to reliably provide such contacts is not yet in place. Therefore, there is still a great need for the ability to control the slope of the contact walls so as to permit good step coverage and contact to the lower conductive layer by the overlying conductive layer.